Static Random Access Memory (SRAM) cells are the basic building blocks of many memories. An exemplary conventional 6-transistor (6T) SRAM cell as illustrated in FIG. 1 comprises two cross-coupled inverters, each inverter comprising a serially-connected P-channel Field Effect Transistor (PFET) and N-channel Field Effect Transistor (NFET), which allows the 6T SRAM cell to store one bit of data. The 6T SRAM cell also comprises two NFET pass-gate transistors which allow reading data from and writing data into the 6T SRAM cell. A conventional memory circuit may incorporate multiple individual 6T SRAM cells.
Memories using 6T SRAM cells are commonly used as cache memories in microprocessors, digital signal processors (DSPs) and other integrated circuits. As semiconductor processes scale to smaller and smaller minimum feature sizes, the performance of the 6T SRAM cell does not always improve as much as the performance of the integrated circuits that rely on memories that employ the 6T SRAM cell. It is therefore desirable to increase performance of the SRAM cells. One conventional technique used to increase performance is to replace the 6T SRAM cell with an 8-transistor (8T) SRAM cell as illustrated in FIG. 2. The 8T SRAM cell illustrated in FIG. 2 provides separate read and write paths for the bit of data stored in the 8T SRAM cell. The 8T SRAM cell increases performance at the cost of increased leakage power due to the two additional transistors.
It is also desirable to reduce leakage power in order to reduce the overall energy usage of an integrated circuit. Since cache memories commonly can represent a significant portion of an entire integrated circuit and SRAM cells can represent a large portion of a cache memory, it is especially desirable to be able to reduce leakage power of the SRAM cells and consequently of the integrated circuit as a whole.
It is therefore desirable to develop techniques that increase performance and reduce leakage in SRAM cells.